The Network Designer’s Handbook

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Editors
Thompson, P., Jones, A.M., Davies, S.R., Firch, M.A., Wright, C.J.
Pub. date
January 1997
Pages
309
Binding
softcover
Volume
51 of Concurrent Systems Engineering Series
ISBN print
978-90-5199-380-6
Subject
Computer & Communication Sciences, Computer Science
€84 / US$93 Excl. VAT
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The Network Designer's Handbook will help anyone trapped between limited bandwidth, fault-intolerant computer buses and expensive, over-engineered telecommunications technology. It will help anyone looking for new cost-effective ways to build LAN switches, RAID systems, multimedia servers
or multiprocessors. It will help the small company looking for an edge to break into the market, and the large one looking for ways to improve its margins and boost its market share. This handbook, the result of over six man-years of effort at the PACT Research Institute, provides solid engineering data for the computer systems professional. Four cpu-months of system simulation are summarised in an easy-to-read form, allowing the consequences of different design decisions to be simply compared.
The Network Designer's Handbook explains the principles of the new generation of small-scale low-buffer serial interconnects. Using the specific example of IEEE 1355-1995 links and the STC104 high-valency switch chip it shows how this technology can provide modular, fault-tolerant and scalable
interconnect. The picture is rounded out with descriptions of network topologies, case studies and many practical tips.