IOSPress

This dissertation describes the Delft-Java architecture and the mechanisms required to dynamically translate JVM instructions into Delft Java instructions. Using a form of hardware register allocation, we transform stack bottlenecks into pipeline dependencies which are later removed using register renaming and interlock collapsing arithmetic units. The hardware requirements to perform this translation are not excessive when support for Java language contracts are incorporated into the processor's ISA. When combined with superscalar techniques and multiple instruction issue, we remove up to 60% of translated dependencies. When compared with a realizable stack-based implementation, our approach accelerates a Vector Multiplity execution by 2.7x when hardware constraints were considered. Because this approach requires minimal additional hardware for Java translation, it is an efficient technique for executing Java bytecode.